The present invention relates to an inverter device. More particularly, the invention relates to an inverter device employing semiconductor current control elements.
FIG. 1 shows a typical example of a conventional inverter device of the same general type to which the invention pertains. The device includes a first field effect transistor (MOSFET) 2 having a drain 2a connected to a positive terminal of a power source 1 and a source 2b connected to a drain 3a of a second MOSFET 3, the source 3b of which is connected to a negative terminal of the power source 1 to form a closed circuit. Gates 2c and 3c of the first and second MOSFETs 2 and 3 are connected to gate drive circuits 4 and 5, respectively. In FIG. 1, reference numeral 30 indicates an output terminal of the device.
When the first and second MOSFETs 2 and 3 are used as switching elements, an equivalent circuit of the device is as shown as in FIG. 2, in which there are capacitances C.sub.1, C.sub.2 and C.sub.3 present between the drain 2a and the gate 2c, between the gate 2c and the source 2b and between the drain 2a and the source 2b, respectively. A resistor R, which appears when the first MOSFET 2 is turned on, is connected in series with a switch SW which is controlled by a voltage between the source 21 and the gate 2c. Further, the circuit includes a diode D connected in the reverse direction between the drain 2a and the source 2b. SITs (Static induction transistors) or junction-type field effect transistors etc. may be used instead of MOSFETs.
In operation, when the first MOSFET 2 is turned on upon reception of an output of the gate drive circuit 4, the potential at the output terminal 30 becomes equal to a potential V.sup.+ of the power source 1. Then, when the first MOSFET 2 is turned off and the second MOSFET 3 is turned on upon reception of an output of the gate drive circuit 5, the potential at the output terminal 30 changes from V+to V.sup.31 . That is, the voltage between the drain 3a and the source 3b of the second MOSFET 3 changes from V.sup.+ to 0 and the voltage between the drain 2a and the source 2b of the first MOSFET 2 increases to V.sup.+ abruptly.
FIGS. 3A through 3G taken collectively a timing chart describing the operation of the device of FIG. 1, of which FIG. 3A shows the switching state of the first MOSFET 2 and FIG. 3B that of the second MOSFET 3. FIG. 3C shows the potential at the output terminal 30, FIG. 3D the drain current of the first MOSFET 2, FIG. 3E the drain current of the second MOSFET 3, FIG. 3F the voltage between the source 2b and the gate 2c of the first MOSFET 2, and FIG. 3G the voltage between the source 3b and the gate 3c of the second MOSFET 3.
As can be seen from the waveform of FIG. 3E a current spike IO.sub.2 is produced by the current flowing through the electrostatic capacitances C.sub.1 to C.sub.3 in FIG. 2 when the second MOSFET 3 is turned on. A current spike IO.sub.2 is also produced when the first MOSFET 2 is turned on, as shown by FIG. 3D. Due to the current spikes IO.sub.2 and IO.sub.1, voltage drops V.sub.1 and V.sub.2 are produced across the capacitance C.sub.2 as shown by the waveforms of FIGS. 3F and 3G, respectively. When the voltage drops V.sub.1 and V.sub.2 reach threshold voltages V.sub.+h1 and V.sub.+h2 of the first and second MOSFETs 2 and 3, the switch SW in FIG. 2 is switched on to provide a time period during which both the first and second MOSFETs 2 and 3 are conductive, resulting in a chort circuiting of the power source 1.
In the conventional inverter using the first and second MOSFETs 2 and 3 and constructed as above, when one of the FETs is turned on, current spike occurs which causes the other FET, then in the nonconductive state, to be turned on, thereby shortcircuiting the power source 1. Accordingly, the MOSFETs and the power source 1 may be damaged.
FIGS. 4A through 4C show waveforms of the voltage between the drain 3a and the source 3b of the second MOSFET 3 with a load connected to the output terminal 30 being inductive, resistive and capacitive, respectively, and FIGS. 4D and 4E show corresponding operational states (on and off) of the first and second MOSFETs 2 and 3, respectively.
The MOSFETs 2 and 3 are switched between on and off states by the output signal of the gate drive circuits 4 and 5, respectively. For example, when the FETs are supplied with output signals such that the first and second MOSFETs 2 and 3 are turned off and on, respectively, the potential at the output terminal 30 becomes that (V.sup.-) of the negative terminal of the power source 1, whereupon a current I flows through a load connected to the output terminal 30.
If the load is inductive, when the second MOSFET 3 is turned off at a time instant t.sub.1, a current I.sub.2 designated in FIG. 1 continues to flow through the load due to the fact that a current tends to flow in the same direction as that just before turn-off, and thus the potential at the output terminal 30 becomes V.sup.+. A surge voltage S.sub.L is very small in this case (see FIG. 4A). There may be substantially no surge voltage produced when the MOSFET 2 is turned on at a time instant t.sub.2 since the potential at the output terminal 30 is then at the potential of the positive terminal of the power source.
If the load is resistive, when the MOSFET 3 is turned on at the time instant t.sub.1, the potential at the output terminal 30 becomes V.sub.M, which is between V.sup.+ and V.sup.-. Then, when the MOSFET 2 is turned on at t.sub.2, the potential at the output terminal 30 increases abruptly. Since the shift of the MOSFET 2 to the on state is performed at a very high speed, a surge voltage S.sub.R is produced due to an oscillation of an oscillation circuit composed of a distributed inductance and stray capacitance of the circuit wiring and the electrostatic capacitances of the MOSFET etc. (see FIG. 4B).
If the load is capacitive, when the MOSFET 3 is turned off at t.sub.1, the potential at the output terminal 30 does not change substantially. Then, when the MOSFET 2 is turned on at t.sub.2, the potential at the output terminal at the output terminal 30 increases abruptly. Particularly, a surge voltage S.sub.c produced in this case is higher than that S.sub.R in the case of a resistive load because of a higher voltage increase rate dV/dt due to the high switching speed of the MOSFET.
As mentioned above, the surge voltage produced in the conventional inverter is very high, and if it is higher than the breakdown voltage of the MOSFET, the latter may be destroyed. Thus, it has been difficult to construct an inverter using high voltage MOSFETs having high switching speeds.